**Yu. Yu. Kolbas, I. V. Dronov**

Study of High-Precision Analog-To-Digital Converter for Measuring Current-Output Accelerometer Signal

DOI: 10.22184/1993-7296.2018.12.7.684.694

For the modern inertial navigation systems, the measurement of acceleration is very important. According to the accelerometer readings, the initial calibration of the system is made, i. e. the determination of the roll and pitch angles before the movement and the calculation of the linear coordinates during the movement. The accelerometer channel of the inertial navigation system (INS) consists of the accelerometer itself and the converter of its output signal into a digital form (code). There are many types of converters for converting analog signals into the code – analog-to-digital converters (ADC): integrating based on current-frequency converters, direct conversion, sigma-delta, etc. All of them have their advantages and disadvantages becoming critical under conditions of short conversion time and temperature effects. The purpose of this paper is to analyze the existing ADCs and their suitability for operating under such conditions in the accelerometer channel of the inertial navigation system of dynamic objects in order to construct the most optimal ADC for this application.

1.

Requirements for the ADC of the INS accelerometer channel and various types of ADCs

The output signal of the accelerometer is usually the current passing through the reference resistor. Therefore, it is possible to use 2 types of converters: accelerometer current – code and voltage on the accelerometer load resistor – code. A number of specific requirements are specified to the ADC accelerometer channel ANN:

• a large range in the amplitude of the input signal (from units of microvolts to 10 volts);

• the accuracy of the measurement is not worse than 0.001% (not less than 18 binary digits considering the sign);

• consistency of characteristics over a wide range of temperatures;

• since for the calculation of linear coordinates a double time integral is used from the measured acceleration, the ADC should operate in the continuous measurement mode of acceleration "a" for the time interval for issuing the information (Fig. 1) [1];

• sufficient dynamic range of frequencies of measured accelerations, exceeding by an order of magnitude the frequency range of accelerations of the object with the accelerometers installed.

From the functional point of view, an ADC with continuous integration is necessary for working with accelerometers. The variant of the circuit of such ADC is shown in Fig. 2 [2].

In the inverting input of the integrator, consisting of the operational amplifier OA and the capacitor C, the output current of the accelerometer Iacc flows. At the beginning of each measurement cycle, the control circuit of the control unit checks the state of the comparator Com and supplies a positive or negative voltage ± Uop through the analog key AK and the resistor R for the integrator zeroing to the integrator’s input. The zeroing time of the integrator will be proportional to the current Iax accumulated over the measurement interval. When the zero voltage on the output of the integrator Y is reached, the control circuit CC cuts the resistor R from the corresponding reference source, i. e. the current from the accelerometer Iax is balanced by the current caused by applying voltage Uop to the inverting input of the amplifier. In steady state, the following condition must be satisfied:

, (1)

, (2)

. (3)

Expression (3) shows that the accuracy of the conversion is determined by the accuracy of the setting of Uop, the accuracy of holding the pulse duration Uop, and the accuracy of the resistor R. The capacitance of the integrator capacitor does not affect the finite accuracy of the measurement.

Advantages of this ADC circuit are as follows:

• there is no need for a low-pass filter at the accelerometer output;

• the ADC performs one measurement per control cycle, which simplifies data processing in the system.

The accuracy of the conversion will be determined by the stability of the integrator, the reference sources of the voltage and their symmetry, the through resistance and the zero offset of the analog key. The zero offset of such a converter reaches ± 100 µV, the nonlinearity and instability of the conversion coefficient is ± 0.01% against the required ± 0.001%. As a result, such ADCs are only used in low-precision INS, where low mass and power consumption of electronic blocks are required. Popular ADCs with bitwise balancing have an accuracy of not better than 0,005% (16 bits), which does not meet the previously formulated requirements for the INS accelerometer channel – at least 0.001%. The ADCs with push-pull integration meet the accuracy requirements, but have conversion time, depending on the amplitude of the input signal, which is inadmissible, since the navigation task solution is performed with a rigid time step. In such an ADC, the signal conversion process can be described by the following equation:

. (4)

Thus, none of the considered ADC types fully satisfy the requirements for the INS accelerometer channel.

SIGMA-DELTA ADCS WITH PERIODIC CALIBRATION OF ZERO OFFSET

In recent years, the sigma-delta ADC architecture has become increasingly popular for high-resolution ADCs. Its name is due to the presence of two units: "sigma" – integrator, "delta" – differential amplifier. The main principle embodied in these converters and allowing to increase the resolution is the averaging of the measurement results [3]. The first-order ΣΔ-ADC circuit is shown in Fig. 3.

The operation principle of this ADC is somewhat more complex than that of other types of ADCs. Its essence is that the input voltage on the reference resistor, through which the output current of the accelerometer flows, is compared with the value of the voltage accumulated by the integrator.

The voltage of the positive or negative polarity is applied to the integrator input, depending on the comparison result. Thus, this ADC is a simple tracking system: the voltage at the output of the integrator "monitors" the input voltage (Fig. 4). The result of this circuit is a stream of zeroes and ones at the output of the comparator, which is then passed through a digital low-pass filter (LPF). The LPF is usually combined with a decimator, a device that reduces the sampling rate by "thinning" them.

In the simplest case, to obtain the N-bit code at the output, it is necessary to sum the one-bit sequence produced by the comparator within 2N clock cycles. The purpose of this summation is to obtain the average value of the measured value for this time interval. In the actual devices, a more efficient from the point of view of performance is the method of obtaining the average value of the measured value: the use of high-order digital filters.

It should be noted that first-order ΣΔ-ADCs are not currently used anywhere due to a number of advantages of higher-order converters.

The most serious disadvantage of the ΣΔ-ADC is the dependence of the conversion scale on temperature and clock frequency, which leads to the need for regular calibration of the device. This dependence is caused by the impossibility of manufacturing in the K-MOS-schemes of condensers with a stable value of the capacitors of the integrators that determine the scale. As a rule, modern chips of ΣΔ-converters have embedded nodes for calibration, which simplifies this procedure.

Another disadvantage, limiting the use of ΣΔ-ADC, is the impossibility of lockstep synchronization with the signal. Let’s remind that the device includes a filter that suppresses high-frequency components of the signal and offsets it in time. Therefore, it is rather problematic to accurately classify the received readings at a fixed time moment. Nevertheless, at present there is a fairly wide range of ΣΔ-ADCs in the integrated version with the ability to work in a wide temperature range, and their disadvantages can be compensated by modern means of digital technology. Fig. 5 shows a functional three-channel ADC circuit for working with accelerometers on modern ΣΔ-converters.

ADS1259 (Texas Ins.) has been selected as ADC, having the following basic characteristics:

• 24-bit capacity,

• data rate – up to 14,400 measurements per second

• the range of input voltages ±2,5 V,

• the nonlinearity of the conversion is not worse than ±0,0003% of the full scale.

Besides the actual ΣΔ-converter, the ADC comprises a programmable digital filter, calibration scheme and high-speed serial interface for coupling with the processor. The peculiarity of this ADC is the possibility of connecting the measured common-mode voltages with symmetry with respect to ground, which simplifies coupling with the accelerometers. More common ADCs with positive common-mode voltage require a level-offset circuit, which in this case can lead to zero-offset errors.

A low-pass filter with a cutoff frequency of 200 Hz is embedded in each ADC input. As a filter, the 2nd order Butterworth filter is selected. The peculiarity of this filter is that it has a single transmission factor for direct current, independent of the filter parameters. This allows you to exclude the effect of the filter on the converter’s scale factor stability.

The accelerometer having a current output is loaded with a precision resistor and interfaces with the filter through an attenuator consisting of a precision resistive divider with a coefficient of ¼, repeaters on the OA, and an analog switch controlled by the CPU. In addition to the measured inputs, a reference voltage and analog ground are input to the analog switch, which allows calibrating the ADC. In fact, each channel has two ranges: ± 10g and ± 40g. This approach allows you to increase the integral accuracy in the system, since most of the time it is necessary to measure the acceleration in the range ± 10g – when measuring in this range the input divider is disconnected and does not introduce errors in the resulting accuracy of the ADC. The ADC conversion frequency is selected to be 14,400 samples per second; the internal filter is configured to output to the processor at a speed of 1200 samples per second. At the processor level, additional accumulation and filtering are performed, with data output to the system via the ISA-PC104 bus at a frequency of 200 Hz. By the sampling theorem, this approach allows to reduce the noise level of the ADC by at least 8 times.

The problem of binding the data output from the ADC to the grid of the system is solved by forming the reference frequency of the ADC on a programmable logic integrated circuit (PLIC). An internal PLIC frequency synthesizer and additional digital logic that binds to the external synchronization of 200 Hz is used.

In addition, the interface with temperature sensors of accelerometers is implemented on the ADC module, the account for the temperature model of accelerometers makes it possible to increase the accuracy of measuring accelerations. Temperature sensors through the interface circuit are connected to the embedded ADC of the CPU, which has a precision of 12 bits. After conversion and scaling, the temperature data is output to an external bus with reference to acceleration data.

To obtain the accuracy of the ADC based on the ΣΔ-converter, a calibration procedure with respect to the zero offset and the scale factor is necessary. For the chosen ADC, the task is simplified by the availability of support means on the chip of the microcircuit. The correction values of the zero offset and the scale factor obtained during calibration are stored and used when correcting the output data directly at the level of the ADC chip.

When the ADC module is turned on, the calibration procedure is performed automatically. When working in the system, it is advisable to carry out calibration periodically, with a significant temperature change. Since the calibration is performed for a sufficiently long time, up to 50 ms (10 cycles) with the selected ADC modes, the output of the sample data can be approximated by the processor of the module in order to obtain correct output data.

A useful solution to the problem of storing information about acceleration during calibration is parallel connection of ADC modules with alternate calibration of each module while the system is running.

3.

EXPERIMENTAL STUDY OF THE SIGMA-DELTA ADC WITH PERIODIC ZERO OFFSET CALIBRATION

Let’s consider the experimental results of the ADC implementation given in Fig. 6 shows the temperature dependences of the relative deviation of the conversion factor dK for two ADC channels from a single value:

dK = Ki – 1. (5)

Figures 7 and 8 show the temperature dependences of the zero offset Sa both with and without periodic calibration. The generalized results of the experiment are given in Table.

Thus, the use of periodic calibration allows you to reduce the zero- offset error up to 18 times. The most effective use of the approximating function with a fourth-order polynomial of temperature is:

Sa (T) = K1 · Т4 + K2 · Т3 + K3 · Т2 + K4 · Т + К5 (6)

Figures 9 and 10 show the dependence of the conversion factor K and the displacement of zero Sa on frequency of the variable input signal from the accelerometer f.

As can be seen from the figures, the frequency range of the ADC over K level of 0,7 is 0,45 · fo (fo is the frequency of information transfer from the ADC). That is, at a sampling frequency of the ADC of 1000 Hz, we received an acceptable error when measuring a signal with a frequency of up to 450 Hz. If we start from the zero- offset error, then the correct criterion for limiting the frequency range is the achievement of a relative error in the zero offset of the value of the nonlinearity of the transformation. In our case, assuming a nonlinearity equal to 1,4 · 10–4 rel. unit, we obtain a frequency range of 0,55 · fo. At a sampling frequency of 1000 Hz, this is 550 Hz. Given that modern accelerometers have a frequency range of up to 300 Hz [5], the ADC under study has an ample frequency conversion range.

CONCLUSION

Thus, for measurement of accelerometer signals, the ΣΔ-ADC with channel duplication is the most attractive, combining both a small error of the measured acceleration integral and a high information conversion frequency with an acceptable conversion factor error. It is shown that the use of temperature-algorithmic correction makes it possible to reduce the change in the zero shift of the ADC by 18 times. To obtain the highest characteristics, the temperature sensor should be included in the ADC, which makes it possible to realize a temperature approximation of the errors, first of all, a zero offset.