rus
Issue #8/2024
A. E. Gabdrakhmanov, E. N. Rybachek, E. M. Yeganova, D. V. Ryazantsev, N. V. Komarova, A. E. Kuznetsov
Development of Charge Trapping SONOS Memory Cells
Development of Charge Trapping SONOS Memory Cells
DOI: 10.22184/1993-7296.FRos.2024.18.8.598.607
In this paper, a process for creating a SONOS memory cell with an improved structure within
the CMOS route according to 1.5 μm process standards that can be integrated to silicon
photonics is proposed. The resulting memory has a write voltage of 12 V and an erase voltage
of –13 V. The write speed is 80 ms. The memory window is more than 3 V with a working
window of 2 V.
Subscribe to the journal Photonics Russia to read the full article.
In this paper, a process for creating a SONOS memory cell with an improved structure within
the CMOS route according to 1.5 μm process standards that can be integrated to silicon
photonics is proposed. The resulting memory has a write voltage of 12 V and an erase voltage
of –13 V. The write speed is 80 ms. The memory window is more than 3 V with a working
window of 2 V.
Subscribe to the journal Photonics Russia to read the full article.
Readers feedback
