rus
Issue #8/2024
A. E. Gabdrakhmanov, E. N. Rybachek, E. M. Yeganova, D. V. Ryazantsev, N. V. Komarova, A. E. Kuznetsov
Development of Charge Trapping SONOS Memory Cells
Development of Charge Trapping SONOS Memory Cells
DOI: 10.22184/1993-7296.FRos.2024.18.8.598.607
In this paper, a process for creating a SONOS memory cell with an improved structure within
the CMOS route according to 1.5 μm process standards that can be integrated to silicon
photonics is proposed. The resulting memory has a write voltage of 12 V and an erase voltage
of –13 V. The write speed is 80 ms. The memory window is more than 3 V with a working
window of 2 V.
In this paper, a process for creating a SONOS memory cell with an improved structure within
the CMOS route according to 1.5 μm process standards that can be integrated to silicon
photonics is proposed. The resulting memory has a write voltage of 12 V and an erase voltage
of –13 V. The write speed is 80 ms. The memory window is more than 3 V with a working
window of 2 V.
Development Of Charge Trapping SONOS Memory Cells
A. E. Gabdrakhmanov 1, E. N. Rybachek 2, E. M. Yeganova 1, D. V. Ryazantsev 1, N. V. Komarova 1, A. E. Kuznetsov 1
Design Center "Heterogeneous integration", Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences
Scientific-Manufacturing Complex "Technological Centre"
In this paper, a process for creating a SONOS memory cell with an improved structure within the CMOS route according to 1.5 μm process standards that can be integrated to silicon photonics is proposed. The resulting memory has a write voltage of 12 V and an erase voltage of –13 V. The write speed is 80 ms. The memory window is more than 3 V with a working window of 2 V.
Keywords: non-volatile memory, charge trapping memory, SONOS, electrophysical characteristics of the memory cell, silicon photonics
Article received: 14.11.2024
Article accepted: 28.11.2024
INTRODUCTION
The need for devices with non-volatile memory (NVM) is constantly increasing. Some applications require the devices characterized with high energy efficiency or radiation resistance [1, 2]. In this regard, the development of alternatives to classical flash memory is required. The emergence of silicon photonic technology makes it possible to expand the possibility of using non-volatile memory in the field of optical signaling, modulation, switching, filtering and others [3, 4] to create photonic memory, resonators and interferometers. Photonic data storage would significantly improve the performance of existing computing architectures by reducing delays associated with electrical memory and potentially eliminating optoelectronic transformations. In addition, the use of non-volatile charge storage memory in nanophotonic resonators would allow their resonance to be tuned by changing the concentration of free charge carriers in the silicon layer of nanoscale waveguides [3].
Classic flash-memory cells are based on floating gate transistors [5]. Charge trapping memory cells are an alternative to them [4, 5]. Besides, nanocrystalline memory is sometimes considered as a separate subtype of memory cells [5].
Floating Gate (FG) memory is the most popular solution [2,5], although FG memory is inferior in many characteristics to charge trapping memory [5]. Its dominance in the NVM device market is due to its earlier appearance, a large amount of research with its implementation in production and subsequent commercialization, and a simple storage principle [5]. A floating gate memory cell is a MOSFET in which the standard gate dielectric consists of a polysilicon layer sandwiched between two dielectrics, in which the charge is stored [6,7]. Fig. 1a shows a schematic diagram of a standard cell of such memory.
In charge trapping memory, unlike FG memory, a dielectric layer [5], such as silicon nitride [1, 6], is used to store the charge. The charge itself is captured by traps during injection or tunneling. An example of the structure of such a memory cell is shown in Figure 1b. Such memory has several advantages over FG memory, namely [1, 5]:
higher durability, at least one to two orders of magnitude higher than that of FG cells (≈107 write/erase cycles);
lower write and erase voltages, usually almost twice as low as for FG memory devices;
simplified cell structure compared to FG memory, requiring fewer photolithographs [6];
double bit density. Due to the discrete and local storage of charges in the charge storage layer, the same cell can be used to store 2 bits of information. During the injection of hot carriers, these are stored at the area near the drain. If the source and drain are interchanged after writing, two areas for writing appear, and can be read afterwards. Thus, the charge trapping layer on both sides will have different states due to local charge storage. This is an alternative solution for increasing the bit density in a cell;
radiation resistance due to charge storage on traps compared to FG devices, in which the charge is stored in the polysilicon volume.
Different materials can serve to form charge trapping memory cells; the characteristics of these materials should fit the functions of each layer. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, [8]) memory is a classic variant of charge trapping memory [1,6]. Such a memory cell is a transistor with modified gate dielectric. The structure of the charge trapping memory is divided into 5 layers (Fig. 1b): c-Si substrate, tunnel oxide (SiO2), charge trapping layer (Si3N4), blocking oxide (SiO2) and control gate (poly-Si).
The operating principle of this memory includes three functions: writing, erasing and reading. During the writing through the lower oxide, electrons tunnel into the charge storage layer, where they are captured by traps, which in turn increases the threshold voltage value. When erasing through the lower oxide, holes tunnel into the charge storage layer, reducing the threshold voltage. When reading, it is determined whether the transistor is open or closed, which is interpreted as writing "zero" or "one" to the transistor cell at the current time when using the transistor.
In this paper, a process for production of a gate structure for SONOS memory compatible with the 1.5 µm CMOS IC manufacturing technology was developed. Test SONOS memory cells were obtained. Their electrophysical characteristics were studied, the dependences of the write/erase voltage on the layer thickness and the concentration of tunnel oxide defects were investigated, the write/erase speeds and the spread of memory windows were calculated. The concentration of traps in silicon nitride was estimated.
METHODS
p-Type (1 0 0) bulk silicon wafers were used to manufacture crystals with memory cells. The following reagents were used for chemical treatment: buffer etchant ammonium hydrofluoride (NH4F + HF), peroxide-hydrochloric acid solution (PHS, HCl : H2O2 : H2O), solution of diluted hydrofluoric acid (HF 1 : 50) and peroxide-ammonia solution (PAS, NH4OH : H2O2 : H2O). Liquid chemical ammonia (NH3) and dichlorosilane (SiH2Cl2) were used for silicon nitride deposition. Tetraethoxysilane (TEOS, (C2H5O)4Si), oxygen and gaseous argon, liquid chemical ammonia were used for barrier oxide deposition. The memory cells were manufactured using 1.5 μm CMOS technology.
Before forming multilayer dielectric layers, chemical preparation of the initial surface of the silicon substrate was performed. The preparation included four operations: etching of the pre-grown oxide in a buffer etchant, processing in PHS, processing in HF 1 : 50 and processing in PAS.
A two-stage process was used to obtain tunnel silicon oxide. First, thermal oxide was grown in oxygen at a temperature of 850 °C in the SDOM‑3/100-003 diffusion single-zone system. Then the oxide layer was thinned to a specified thickness by washing in a hydrofluoric acid solution.
The charge trapping layer (Si3N4) was obtained by chemical vapor deposition (CVD) in an HCVD‑55 device at 780 °C using the process of pyrolytic decomposition of NH3 and SiH2Cl2 mixture.
The blocking silicon oxide layer was obtained by the CVD method in the Isotron‑4 device at 730 °C. TEOS mixed with oxygen was used as a precursor. After deposition of the silicon oxide layer, two annealing stages were performed: in ammonia plasma at 400 °C in HCVD‑52, and then in an oxygen environment at 850 °C in SDOM‑3/100-003.
The films obtained after the technological processes were characterized using a SENTECH SENDIRA ellipsometer. The gate of the obtained structures was examined using a TEM (JEM‑2100 plus, Jeol). The electrical parameters of the structures, such as current-voltage characteristics, voltage, and recording and erasing speed, were measured using a semiconductor analyzer (B1500A, Agilent) and a probe station (PM5, Cascade).
RESULTS AND DISCUSSION
The SONOS memory cell is a MOSFET structure in which the gate dielectric consists of a charge trapping layer sandwiched between two oxide layers (Fig. 1b). In this paper, a memory cell fabrication process based on the CMOS route was proposed. The gate formation step of the original CMOS route was supplemented with operations to create a multilayer dielectric structure.
Fig. 2a illustrates a schematic representation of the gate structure with the initially selected layer thicknesses and materials. Thermic silicon oxide with a thickness of 25 Å was selected to serve as the tunnel oxide. The choice of such a thickness arises from the following factors. The tunnel oxide layer should be thin enough to reduce the voltage for writing and erasing, but at the same time its thickness should be large enough to avoid spontaneous quantum tunneling through the layer. The minimum thickness of the silicon oxide-based tunnel layer should be 18–20 Å [9, 10]. However, at such values, the non-uniformity of the layer thickness increases, so the thickness of the tunnel layer in the designed cell was set to be larger, taking into account the expected deviation. A silicon nitride film with a thickness of 10 nm was chosen as the charge trapping layer. This layer thickness resulted from the consideration that it should be minimal while maintaining sufficient density of charge traps [1]. A two-layer structure consisting of 8 nm thick silicon oxide and 4 nm thick silicon oxynitride was used as a blocking layer, which acts as a barrier to minimize retention losses and unwanted charge injection from the gate. The use of an additional silicon oxynitride layer minimizes charge leakage into the gate compared to a single SiO2 barrier layer without increasing the write and erase voltage [1].
Before forming multilayer dielectric layers, the initial surface of the silicon substrate was chemically treated. The treatment includes four operations. At the first stage, pre-grown oxide is etched in a buffer etchant. Then, treatment in PHS is carried out to clean the silicon surface from alkali metal ions and some transition metals [11]. After PHS, an uneven layer of silicon oxide with a thickness of 1–3 nm on the surface of the wafer is formed, which includes defect formation centers. To remove this, hydrofluoric acid treatment was carried out. Then, PAS treatment is used to remove organic contaminants and metal ions and reduce the defectiveness of the silicon surface [11].
After chemical treatment, a thermic oxide with a thickness of 18 nm was grown, and then thinned to 2–3 nm by etching in hydrofluoric acid. The thicknesses of all layers during menufacturing were controlled using ellipsometry.
Next, a silicon nitride layer was grown. Ellipsometry results indicate that the thickness of the Si3N4 layer obtained by the CVD method was 10–12 nm.
A 12 nm thick SiO2 layer was formed by the CVD method. A portion of the oxide was converted into SiOxNy oxynitride by successive annealing in ammonia and oxygen plasma. For optical applications, the above-mentioned thickness of the MOS insulating layer of about 12 nm is insufficient due to ohmic losses in the gate [3]. To avoid excessive optical losses, the thickness of the top oxide layer above the nitride layer should be increased. Increasing the layer thickness will require working with higher voltages for charge trapping/erasing. In this work, the barrier layer thickness was chosen low (12 nm) for compatibility with the existing equipment for studying the properties of the memory cell.
The obtained cells were examined using the TEM method. Fig. 2c shows a cross-section of the multilayer gate structure. The structure of the original single-crystal silicon can be seen. It is followed by amorphous thermic silicon oxide with a thickness of about (2.5 ± 0.5) nm. On top of it a layer of amorphous silicon nitride with a thickness of (11 ± 1) nm is presented followed by the residual amorphous silicon oxide from TEOS (8 ± 1) nm. The structure is covered by a film of silicon oxynitride with a thickness of (4 ± 1) nm, which was formed after annealing in ammonia.
To determine the minimum and working values of the write and erase voltage, the dependences of the threshold voltage on the write and erase voltage were recorded. The write voltage was varied in the range from 6 to 12 V with a step of 1 V; the write time was 10 ms. The erase voltage was changed from –8 to –15 V with a step of 1 V with a write time of 10 ms. Additionally, to determine the memory window, the erase process was performed at a voltage of –15 V for 100 and 1 000 ms. The obtained dependences of the threshold voltage on the write / erase voltage (their absolute values for clarity) are shown in Fig. 3.
As can be seen from Figure 3, the threshold voltage shift occurs at a write voltage of 9 V. Then the rate of threshold voltage growth increases up to a write voltage of 13 V. With a further increase in the write voltage, the memory cell is saturated. The optimal voltage for writing is 12 V. From the erase curve, it is clear that the erase process begins at a voltage of –11 V. The erase rate slowly increases up to a voltage of –14 V and almost does not change for an erase voltage of –15 V. An erase voltage of –13 V was optimal.
Table 1 shows the write and erase voltages for SONOS memory cells produced using process technologies with different geometry rules. The data in Table show that the values obtained are close to the average write and erase voltages, and that the parameters used did not vary much from technology to technology and depended primarily on the cell structure rather than its size.
Using the selected write and erase voltages, the dependence of the threshold voltage shift on the write / erase duration was obtained (Fig. 4), from which the write and erase speed was determined. The write time for changing the threshold voltage from –2 to 0.5 V was 80 ms. Erasing in the same range required an order of magnitude more time. A significant increase in the erase time can be compensated for by reducing the memory window. The optimal value of the working memory window was 2 V with average memory window values of 2.5–3.5 V. The value of the working memory window of 2 V is close to the standard [2, 13] in memory cells without silicon nitride with a high trap density [15, 16].
Based on all the data obtained, we can approximately calculate the average trap density in the silicon nitride layer. Each dielectric layer in the gate can be represented as a separate capacitance, and the total capacitance can be calculated using the formula for series-arranged capacitors. Knowing the total capacitance, we can calculate the change in the amount of charge before and after recording from the threshold voltage. After that, we can calculate the amount of charge. Next, neglecting the small effects of the charge outside the silicon nitride on the threshold shift, we can calculate the number of traps in the silicon nitride. The average trap concentration in the silicon nitride calculated in this way was ≈1.1 × 1018 cm−3, which corresponds to the average values (from 5 × 1017 cm−3 to 6 × 1018 cm−3 according to literature data [17]) for silicon nitride without additional modifications used in this type of memory. The possibility of storing charge in a silicon nitride layer has been proven, which allows us to assume that subsequent modification of the barrier layer and gate material will allow this technology to be used for integration into photonic silicon devices in which it is necessary to shift the resonant frequency [3] by changing the surface concentration of charge carriers.
CONCLUSIONS
SONOS memory cells were manufactured using a CMOS route with minimum geometry rules of 1.5 µm. Voltages and write/erase rates were selected and analyzed. The memory window and working memory window, as well as the density of traps in silicon nitride, were determined, with a conclusion about the admissibility of using standard silicon nitride layers in the primary approximation. Further research will be aimed at assessing the charge retention time in the memory cell and expanding the memory window.
ABOUT AUTHORS
A. E. Gabdrakhmanov, amiro202020@gmail.com, process engineer, Design Center "Heterogeneous integration", Institute of Nanotechnology of Microelectronics of the RAS (INME RAS), Moscow.
ORCID: 0009-0002-1195-0944
Rybachek E. N., Senior Researcher, Cand. of Eng. (Tech. Scien.), Scientific-Manufacturing Complex "Technological Centre", Moscow.
ORCID: 0000-0002-3918-4391
Yeganova E. M., Senior Researcher, Cand. of Eng. (Tech. Scien.), Design Center "Heterogeneous integration", INME RAS, Moscow.
ORCID: 0000-0001-6534-4179
Ryazantsev D. V., Senior Researcher, Design Center "Heterogeneous integration", INME RAS, Moscow.
ORCID: 0000-0001-8051-2425
Komarova N. V., engineer, Cand. of Eng. (Chem. Scien.), Design Center "Heterogeneous integration", INME RAS, Moscow.
ORCID: 0000-0002-6148-0971
Kuznetsov A. E., Senior Researcher, Dr. of Eng. (Tech. Scien.), Design Center "Heterogeneous integration", INME RAS, Moscow.
ORCID: 0000-0002-1333-5294
A. E. Gabdrakhmanov 1, E. N. Rybachek 2, E. M. Yeganova 1, D. V. Ryazantsev 1, N. V. Komarova 1, A. E. Kuznetsov 1
Design Center "Heterogeneous integration", Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences
Scientific-Manufacturing Complex "Technological Centre"
In this paper, a process for creating a SONOS memory cell with an improved structure within the CMOS route according to 1.5 μm process standards that can be integrated to silicon photonics is proposed. The resulting memory has a write voltage of 12 V and an erase voltage of –13 V. The write speed is 80 ms. The memory window is more than 3 V with a working window of 2 V.
Keywords: non-volatile memory, charge trapping memory, SONOS, electrophysical characteristics of the memory cell, silicon photonics
Article received: 14.11.2024
Article accepted: 28.11.2024
INTRODUCTION
The need for devices with non-volatile memory (NVM) is constantly increasing. Some applications require the devices characterized with high energy efficiency or radiation resistance [1, 2]. In this regard, the development of alternatives to classical flash memory is required. The emergence of silicon photonic technology makes it possible to expand the possibility of using non-volatile memory in the field of optical signaling, modulation, switching, filtering and others [3, 4] to create photonic memory, resonators and interferometers. Photonic data storage would significantly improve the performance of existing computing architectures by reducing delays associated with electrical memory and potentially eliminating optoelectronic transformations. In addition, the use of non-volatile charge storage memory in nanophotonic resonators would allow their resonance to be tuned by changing the concentration of free charge carriers in the silicon layer of nanoscale waveguides [3].
Classic flash-memory cells are based on floating gate transistors [5]. Charge trapping memory cells are an alternative to them [4, 5]. Besides, nanocrystalline memory is sometimes considered as a separate subtype of memory cells [5].
Floating Gate (FG) memory is the most popular solution [2,5], although FG memory is inferior in many characteristics to charge trapping memory [5]. Its dominance in the NVM device market is due to its earlier appearance, a large amount of research with its implementation in production and subsequent commercialization, and a simple storage principle [5]. A floating gate memory cell is a MOSFET in which the standard gate dielectric consists of a polysilicon layer sandwiched between two dielectrics, in which the charge is stored [6,7]. Fig. 1a shows a schematic diagram of a standard cell of such memory.
In charge trapping memory, unlike FG memory, a dielectric layer [5], such as silicon nitride [1, 6], is used to store the charge. The charge itself is captured by traps during injection or tunneling. An example of the structure of such a memory cell is shown in Figure 1b. Such memory has several advantages over FG memory, namely [1, 5]:
higher durability, at least one to two orders of magnitude higher than that of FG cells (≈107 write/erase cycles);
lower write and erase voltages, usually almost twice as low as for FG memory devices;
simplified cell structure compared to FG memory, requiring fewer photolithographs [6];
double bit density. Due to the discrete and local storage of charges in the charge storage layer, the same cell can be used to store 2 bits of information. During the injection of hot carriers, these are stored at the area near the drain. If the source and drain are interchanged after writing, two areas for writing appear, and can be read afterwards. Thus, the charge trapping layer on both sides will have different states due to local charge storage. This is an alternative solution for increasing the bit density in a cell;
radiation resistance due to charge storage on traps compared to FG devices, in which the charge is stored in the polysilicon volume.
Different materials can serve to form charge trapping memory cells; the characteristics of these materials should fit the functions of each layer. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, [8]) memory is a classic variant of charge trapping memory [1,6]. Such a memory cell is a transistor with modified gate dielectric. The structure of the charge trapping memory is divided into 5 layers (Fig. 1b): c-Si substrate, tunnel oxide (SiO2), charge trapping layer (Si3N4), blocking oxide (SiO2) and control gate (poly-Si).
The operating principle of this memory includes three functions: writing, erasing and reading. During the writing through the lower oxide, electrons tunnel into the charge storage layer, where they are captured by traps, which in turn increases the threshold voltage value. When erasing through the lower oxide, holes tunnel into the charge storage layer, reducing the threshold voltage. When reading, it is determined whether the transistor is open or closed, which is interpreted as writing "zero" or "one" to the transistor cell at the current time when using the transistor.
In this paper, a process for production of a gate structure for SONOS memory compatible with the 1.5 µm CMOS IC manufacturing technology was developed. Test SONOS memory cells were obtained. Their electrophysical characteristics were studied, the dependences of the write/erase voltage on the layer thickness and the concentration of tunnel oxide defects were investigated, the write/erase speeds and the spread of memory windows were calculated. The concentration of traps in silicon nitride was estimated.
METHODS
p-Type (1 0 0) bulk silicon wafers were used to manufacture crystals with memory cells. The following reagents were used for chemical treatment: buffer etchant ammonium hydrofluoride (NH4F + HF), peroxide-hydrochloric acid solution (PHS, HCl : H2O2 : H2O), solution of diluted hydrofluoric acid (HF 1 : 50) and peroxide-ammonia solution (PAS, NH4OH : H2O2 : H2O). Liquid chemical ammonia (NH3) and dichlorosilane (SiH2Cl2) were used for silicon nitride deposition. Tetraethoxysilane (TEOS, (C2H5O)4Si), oxygen and gaseous argon, liquid chemical ammonia were used for barrier oxide deposition. The memory cells were manufactured using 1.5 μm CMOS technology.
Before forming multilayer dielectric layers, chemical preparation of the initial surface of the silicon substrate was performed. The preparation included four operations: etching of the pre-grown oxide in a buffer etchant, processing in PHS, processing in HF 1 : 50 and processing in PAS.
A two-stage process was used to obtain tunnel silicon oxide. First, thermal oxide was grown in oxygen at a temperature of 850 °C in the SDOM‑3/100-003 diffusion single-zone system. Then the oxide layer was thinned to a specified thickness by washing in a hydrofluoric acid solution.
The charge trapping layer (Si3N4) was obtained by chemical vapor deposition (CVD) in an HCVD‑55 device at 780 °C using the process of pyrolytic decomposition of NH3 and SiH2Cl2 mixture.
The blocking silicon oxide layer was obtained by the CVD method in the Isotron‑4 device at 730 °C. TEOS mixed with oxygen was used as a precursor. After deposition of the silicon oxide layer, two annealing stages were performed: in ammonia plasma at 400 °C in HCVD‑52, and then in an oxygen environment at 850 °C in SDOM‑3/100-003.
The films obtained after the technological processes were characterized using a SENTECH SENDIRA ellipsometer. The gate of the obtained structures was examined using a TEM (JEM‑2100 plus, Jeol). The electrical parameters of the structures, such as current-voltage characteristics, voltage, and recording and erasing speed, were measured using a semiconductor analyzer (B1500A, Agilent) and a probe station (PM5, Cascade).
RESULTS AND DISCUSSION
The SONOS memory cell is a MOSFET structure in which the gate dielectric consists of a charge trapping layer sandwiched between two oxide layers (Fig. 1b). In this paper, a memory cell fabrication process based on the CMOS route was proposed. The gate formation step of the original CMOS route was supplemented with operations to create a multilayer dielectric structure.
Fig. 2a illustrates a schematic representation of the gate structure with the initially selected layer thicknesses and materials. Thermic silicon oxide with a thickness of 25 Å was selected to serve as the tunnel oxide. The choice of such a thickness arises from the following factors. The tunnel oxide layer should be thin enough to reduce the voltage for writing and erasing, but at the same time its thickness should be large enough to avoid spontaneous quantum tunneling through the layer. The minimum thickness of the silicon oxide-based tunnel layer should be 18–20 Å [9, 10]. However, at such values, the non-uniformity of the layer thickness increases, so the thickness of the tunnel layer in the designed cell was set to be larger, taking into account the expected deviation. A silicon nitride film with a thickness of 10 nm was chosen as the charge trapping layer. This layer thickness resulted from the consideration that it should be minimal while maintaining sufficient density of charge traps [1]. A two-layer structure consisting of 8 nm thick silicon oxide and 4 nm thick silicon oxynitride was used as a blocking layer, which acts as a barrier to minimize retention losses and unwanted charge injection from the gate. The use of an additional silicon oxynitride layer minimizes charge leakage into the gate compared to a single SiO2 barrier layer without increasing the write and erase voltage [1].
Before forming multilayer dielectric layers, the initial surface of the silicon substrate was chemically treated. The treatment includes four operations. At the first stage, pre-grown oxide is etched in a buffer etchant. Then, treatment in PHS is carried out to clean the silicon surface from alkali metal ions and some transition metals [11]. After PHS, an uneven layer of silicon oxide with a thickness of 1–3 nm on the surface of the wafer is formed, which includes defect formation centers. To remove this, hydrofluoric acid treatment was carried out. Then, PAS treatment is used to remove organic contaminants and metal ions and reduce the defectiveness of the silicon surface [11].
After chemical treatment, a thermic oxide with a thickness of 18 nm was grown, and then thinned to 2–3 nm by etching in hydrofluoric acid. The thicknesses of all layers during menufacturing were controlled using ellipsometry.
Next, a silicon nitride layer was grown. Ellipsometry results indicate that the thickness of the Si3N4 layer obtained by the CVD method was 10–12 nm.
A 12 nm thick SiO2 layer was formed by the CVD method. A portion of the oxide was converted into SiOxNy oxynitride by successive annealing in ammonia and oxygen plasma. For optical applications, the above-mentioned thickness of the MOS insulating layer of about 12 nm is insufficient due to ohmic losses in the gate [3]. To avoid excessive optical losses, the thickness of the top oxide layer above the nitride layer should be increased. Increasing the layer thickness will require working with higher voltages for charge trapping/erasing. In this work, the barrier layer thickness was chosen low (12 nm) for compatibility with the existing equipment for studying the properties of the memory cell.
The obtained cells were examined using the TEM method. Fig. 2c shows a cross-section of the multilayer gate structure. The structure of the original single-crystal silicon can be seen. It is followed by amorphous thermic silicon oxide with a thickness of about (2.5 ± 0.5) nm. On top of it a layer of amorphous silicon nitride with a thickness of (11 ± 1) nm is presented followed by the residual amorphous silicon oxide from TEOS (8 ± 1) nm. The structure is covered by a film of silicon oxynitride with a thickness of (4 ± 1) nm, which was formed after annealing in ammonia.
To determine the minimum and working values of the write and erase voltage, the dependences of the threshold voltage on the write and erase voltage were recorded. The write voltage was varied in the range from 6 to 12 V with a step of 1 V; the write time was 10 ms. The erase voltage was changed from –8 to –15 V with a step of 1 V with a write time of 10 ms. Additionally, to determine the memory window, the erase process was performed at a voltage of –15 V for 100 and 1 000 ms. The obtained dependences of the threshold voltage on the write / erase voltage (their absolute values for clarity) are shown in Fig. 3.
As can be seen from Figure 3, the threshold voltage shift occurs at a write voltage of 9 V. Then the rate of threshold voltage growth increases up to a write voltage of 13 V. With a further increase in the write voltage, the memory cell is saturated. The optimal voltage for writing is 12 V. From the erase curve, it is clear that the erase process begins at a voltage of –11 V. The erase rate slowly increases up to a voltage of –14 V and almost does not change for an erase voltage of –15 V. An erase voltage of –13 V was optimal.
Table 1 shows the write and erase voltages for SONOS memory cells produced using process technologies with different geometry rules. The data in Table show that the values obtained are close to the average write and erase voltages, and that the parameters used did not vary much from technology to technology and depended primarily on the cell structure rather than its size.
Using the selected write and erase voltages, the dependence of the threshold voltage shift on the write / erase duration was obtained (Fig. 4), from which the write and erase speed was determined. The write time for changing the threshold voltage from –2 to 0.5 V was 80 ms. Erasing in the same range required an order of magnitude more time. A significant increase in the erase time can be compensated for by reducing the memory window. The optimal value of the working memory window was 2 V with average memory window values of 2.5–3.5 V. The value of the working memory window of 2 V is close to the standard [2, 13] in memory cells without silicon nitride with a high trap density [15, 16].
Based on all the data obtained, we can approximately calculate the average trap density in the silicon nitride layer. Each dielectric layer in the gate can be represented as a separate capacitance, and the total capacitance can be calculated using the formula for series-arranged capacitors. Knowing the total capacitance, we can calculate the change in the amount of charge before and after recording from the threshold voltage. After that, we can calculate the amount of charge. Next, neglecting the small effects of the charge outside the silicon nitride on the threshold shift, we can calculate the number of traps in the silicon nitride. The average trap concentration in the silicon nitride calculated in this way was ≈1.1 × 1018 cm−3, which corresponds to the average values (from 5 × 1017 cm−3 to 6 × 1018 cm−3 according to literature data [17]) for silicon nitride without additional modifications used in this type of memory. The possibility of storing charge in a silicon nitride layer has been proven, which allows us to assume that subsequent modification of the barrier layer and gate material will allow this technology to be used for integration into photonic silicon devices in which it is necessary to shift the resonant frequency [3] by changing the surface concentration of charge carriers.
CONCLUSIONS
SONOS memory cells were manufactured using a CMOS route with minimum geometry rules of 1.5 µm. Voltages and write/erase rates were selected and analyzed. The memory window and working memory window, as well as the density of traps in silicon nitride, were determined, with a conclusion about the admissibility of using standard silicon nitride layers in the primary approximation. Further research will be aimed at assessing the charge retention time in the memory cell and expanding the memory window.
ABOUT AUTHORS
A. E. Gabdrakhmanov, amiro202020@gmail.com, process engineer, Design Center "Heterogeneous integration", Institute of Nanotechnology of Microelectronics of the RAS (INME RAS), Moscow.
ORCID: 0009-0002-1195-0944
Rybachek E. N., Senior Researcher, Cand. of Eng. (Tech. Scien.), Scientific-Manufacturing Complex "Technological Centre", Moscow.
ORCID: 0000-0002-3918-4391
Yeganova E. M., Senior Researcher, Cand. of Eng. (Tech. Scien.), Design Center "Heterogeneous integration", INME RAS, Moscow.
ORCID: 0000-0001-6534-4179
Ryazantsev D. V., Senior Researcher, Design Center "Heterogeneous integration", INME RAS, Moscow.
ORCID: 0000-0001-8051-2425
Komarova N. V., engineer, Cand. of Eng. (Chem. Scien.), Design Center "Heterogeneous integration", INME RAS, Moscow.
ORCID: 0000-0002-6148-0971
Kuznetsov A. E., Senior Researcher, Dr. of Eng. (Tech. Scien.), Design Center "Heterogeneous integration", INME RAS, Moscow.
ORCID: 0000-0002-1333-5294
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